1. Field of the Invention
The present invention relates generally to a system and method for data transfer to a direct memory access (DMA) input/output (I/O) device which allows a client to access atomically the I/O device. Accessing atomically means that an instruction consisting of more than one individual operation is carried out completely, without interruption for any other operation. More particularly, it relates to such a system and method in a multiprocessor system where multiple processors concurrently access a single I/O device.
An I/O device typically receives data and instructions from the system's main computing resources in one of two ways: either through direct memory-mapped access of I/O registers, or through a DMA mechanism by which the I/O device transfers data directly to and from the main memory subsystem. In either scheme, if the size of the data transfer is larger than an atomic access on the system bus, there are multiple concurrent clients of the I/O device, and the I/O device has a single input stream, there must be a mechanism to synchronize the I/O device among the several clients.
2. Description of the Prior Art
Mutual exclusion of I/O devices, or other shared resources, is typically achieved through software interlocks. Some processor instruction sets contain interlocked instructions, which allow a processor of an I/O device client to perform multiple logical instructions as a single atomic instruction. For example, a processor may test a bit in memory, branch if it is clear, and then set the bit, all within a single instruction. This allows mutual exclusion on shared resources to be implemented through software locks. The I/O device or other shared resource is considered "locked" or unavailable if the bit is set. The process that set the bit "owns" the resource. Systems without interlocked instructions must go through some other atomic protocol, perhaps synchronizing through the operating system or some other unique process.
In particular, graphic subsystems in a multiclient, multiprocessor environment have states maintained internally that are set up in a previous operation and stay for a subsequent operation by the same processor. With interruption by another processor, there is no assurance that those states have been maintained. A technique for executing atomic instructions in this environment is therefore required.